1. Field of the Invention
The present invention relates to programmable logic devices. More particularly, the present invention relates to asynchronously clocking a signal within a synchronously clocked programmable device.
2. Description of the Related Art
Programmable logic devices (PLDs) are popular general purpose logic devices. PLDs generally include an AND array, an OR array and an I/O macrocell. The AND array comprises a plurality of logical AND gates and generates a large number of output signals called AND terms. The AND terms are received by the OR array which comprises a plurality of OR gates. The OR array generates a number of output signals, called product terms, by ORing selected AND terms together. The product terms generated by the OR array are then received by the I/O macrocell which comprises a number of circuit elements including clocked registers. The I/O macrocell of most PLDs outputs signals from the PLD and also feeds output signals back into the AND array for further use.
Many families of programmable logic devices such as PLD, CPLD, FPGA and ASIC devices are synchronously clocked devices. That is, these families of devices have dedicated pins which receive a clock signal for use within the programmable logic device. For example, within a particular family of synchronous programmable logic devices such as the FLASH370.TM. CPLD family provided by Cypress Semiconductor Corporation, clock input signals from dedicated clock/input pins are routed to synchronously clocked programmable registers within an I/O Macrocell. The programmable registers can only be clocked by the dedicated clock inputs.
There does not currently exist, however, a method or apparatus in the architecture of a synchronously clocked programmable device having dedicated system clocks, such as the FLASH370.TM. family, where a signal can be asynchronously clocked without utilizing a register element in an I/O macrocell. This architecture restricts the ability of a designer to use signals other than the dedicated system clocks as clock signals. Additionally, this limits the overall number of clocks available to the designer to the number of dedicated clock input pins.
Other families of PLDs can accommodate asynchronous (or product term) clocking. In these devices, a particular signal generated by the OR array can be utilized, in addition to the dedicated system clocks, to clock a signal through one of the clocked register elements in an I/O macrocell. This function is termed asynchronous clocking because a clock signal other than a dedicated system clock is utilized to clock the synchronously clocked register elements. Alternatively, this function is termed product term clocking because the synchronously clocked register can be "clocked" by a product term signal generated by the AND and OR arrays. In these PLD architectures, the asynchronously clocked signal is clocked through the register element in the I/O macrocell. In general, architectures accommodating product term clocks are inherently slower in operation and are more prone to clock skew and metastability issues in comparison with PLDs having dedicated system clocks.
There does not currently exist, however, a method or apparatus in the architecture of a synchronously clocked programmable which accommodates product term clocking, where a signal can be asynchronously clocked without utilizing a register element in an I/O macrocell.
Therefore, a need exists for utilizing internally or externally generated signals, other than dedicated system clocks, to asynchronously clock signals through a synchronously clocked programmable device without utilizing register elements in the I/O macrocells. Additionally, a need exists for providing a software means for interconnecting programmable logic in a synchronously programmable device having no hardware capability to generate an asynchronous signal, such that an asynchronously clocked signal can be generated.